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Journal papers and books/book chapters - 2015 and 2014

15 Publications found for this search

On the optimality and practicability of mutual information analysis in some scenarios

Cryptography and Communications — Discrete Structures, Boolean Functions and Sequences, January 2018, vol. 10, n° 1, pp. 102-121

Author(s) : E. de Chérisey, S. Guilley, O. Rioul and A. Heuser

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Linear Repairing Codes and Side-Channel Attacks

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018, vol. 2018, n° 1, pp. 118--141

Author(s) : H. Chabanne, H. Maghrebi and E. Prouff

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Optimal Asymmetrical Back Plane Biasing for Energy Efficient Digital Circuits in 28 nm UTBB FD-SOI

Integration, the VLSI Journal, December 2017.

Author(s) : F. Veirano, L. Alves de Barros Naviner and F. Silveira

Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

IEEE Transactions on Circuits and Systems I: Regular Papers, December 2017.

Author(s) : F. Veirano, L. Alves de Barros Naviner and F. Silveira

A Generic Table Recomputation-Based Higher-Order Masking

T-CAD, December 2017

Author(s) : M. Tang, Z. Qiu, Z. Guo, Y. Mu, X. Huang and J.-L. Danger

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Optimal Side-Channel Attacks for Multivariate Leakages and Multiple Models

Journal of Cryptographic Engineering, November 2017, vol. 7, n° 4, pp. 331-341.

Author(s) : N. Bruneau, S. Guilley, A. Heuser, D. Marion and O. Rioul

Analysis of Ageing effects on ARTIX7 XILINX FPGA (article) Author

Microelectronics Reliabilit Journal, October 2017.

Author(s) : M. Slimani, K. Benkalaia and L. Alves de Barros Naviner

Stochastic Collision Attack

IEEE Transactions on Information Forensics & Security, September 2017, vol. 12, n° 9, pp. 2090-2104

Author(s) : N. Bruneau, C. Carlet, S. Guilley, A. Heuser, E. Prouff and O. Rioul

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High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

Applied Science, September 2017, vol. 7, n° 9, pp. 929 (13 pages)

Author(s) : H. Cai, W. Kang, Y. Wang, L. Alves de Barros Naviner, J. Yang and W. Zhao

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PFD - A Flexible Higher-Order Masking Scheme

IEEE transactions on CAD, August 2017, vol. 36

Author(s) : M. Tang, Z. Gou, A. Heuser, Y. Ren, J. Li and J.-L. Danger

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Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

IEEE Transactions on Circuits and Systems I: Regular Papers, April 2017, vol. 64, n° 4, pp. 847-857.

Author(s) : H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao

A Non-Monte-Carlo Methodology for Variability Analysis of Magnetic Tunnel Junction-Based Circuits

IEEE Transactions on Magnetics, March 2017, vol. 53, n° 3, pp. 1-6

Author(s) : Y. Wang, H. Cai, L. Alves de Barros Naviner and W. Zhao

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Cryptographically Secure Shield for Security IPs Protection

IEEE Transcation on Computers, February 2017, vol. 66, n° 2.

Author(s) : X.-Th. Ngo, J.-L. Danger, S. Guilley, T. Graba, Y. Mathieu, Z. Najm and S. Bhasin

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy

Materials Science Journal, January 2017, vol. 9, n° 41, pp. 1-17.

Author(s) : W. Zhao, Y. Wang and L. Alves de Barros Naviner

Privacy-preserving distance computation for IrisCodes

Institution of Engineering and Technology, 2017, pp. 341-358

Author(s) : J. Bringer, H. Chabanne and C. Morel, in

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Conferences and workshops - 2015 and 2014

24 Publications found for this search

Pre-Silicon Embedded System Evaluation as new EDA for Security Verification

International Verification and Security Workshop (IVSW), Platja d’Aro, Spain, June 2018.

Author(s) : S. Takarabt, K. Chibani, Y. Souissi, L. Sauvage, S. Guilley, A. Facon and Y. Mathieu

Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.

Author(s) : F. Veirano, F. Silveira and L. A. B. Naviner

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques

IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.

Author(s) : H. Cai, Y. Wang, L. Alves de Barros Naviner, J. Yang, W. Kang and W. Zhao

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning

To appear in Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, Illinois, USA, May 2018, pp. 23-25.

Author(s) : Y. Wang, Y. Zhang, Z. Youguang, W. Zhao, H. Cai and L. A. B. Naviner

Impact of Aging on Template Attacks

GLSVLSI, Chicago, May 2018

Author(s) : N. Karimi, S. Guilley and J.-L. Danger

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Probability Aware Fault-Injection Approach for SER Estimation

Proceedings of IEEE Latin American Test Symposium (LATS), São Paulo, SP, Brazil, March 2018.

Author(s) : F. B. Armelin, L. Alves de Barros Naviner and R. d'Amore

Using FPGA self-produced transients to emulate SETs for SER estimation

Proceedings of IEEE Latin American Test Symposium (LATS), São Paulo, SP, Brazil, March 2018.

Author(s) : F. B. Armelin, L. Alves de Barros Naviner and R. d'Amore

Analyzing security breaches of countermeasures throughout the refinement process in hardware design flow

DATE, Lausanne, December 2017

Author(s) : J.-L. Danger, S. Guilley, Ph. Nguyen, R. Nguyen and Y. Souissi

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Analysis of Ageing effects on ARTIX7 XILINX FPGA

European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, September 2017.

Author(s) : M. Slimani, K. Benkalaia and L. Alves de Barros Naviner

Sparsity Analysis using a Mixed Approach with Greedy and LS Algorithms on Channel Estimation

International Conference on Frontiers of Signal Processing (ICFSP), Paris, France, September 2017, pp. 91-95.

Author(s) : N. Maciel, E. Crespo Marques and L. Alves de Barros Naviner

Secure Silicon: Towards Virtual Prototyping

EMC Europe 2017, Angers, France, September 2017

Author(s) : L. Sauvage, S. Takarabt, Y. Souissi and N. Homma

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Transforming face-to-face identity proofing into anonymous digital identity using the Bitcoin blockchain

PST2017 - International Conference on Privacy, Security and Trust, Calgary, Canada, August 2017, pp. 10

Author(s) : D. Augot, H. Chabanne, O. Clémot and W. George

pdf  archive 

Stochastic side-channel leakage analysis via orthonormal decomposition

Int. Conf. Information Technology and Communications Security (SECITC 2017), Bucharest, Romania, June 2017

Author(s) : S. Guilley, A. Heuser, T. Ming and O. Rioul

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Formalism to assess the entropy and reliability of the loop-PUF

15th International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices (CryptArchi 2017), Smolenice, Slovakia, June 2017.

Author(s) : J.-L. Danger, O. Rioul, S. Guilley and A. Schaub

A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor

Symposium on VLSI Circuits, Kyoto, Japan, June 2017, vol. Digest of Technical Papers, pp. C266-C267.

Author(s) : N. Miura, K. Matsuda, K. Myszkowski, M. Nagata, S. Bhasin, V. Yli-Mayry, N. Homma, Y. Mathieu, T. Graba and J.-L. Danger

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

VLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on, Bochum, Germany, June 2017.

Author(s) : H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device

Great Lakes Symposium on VLSI 2017 (GLSVLSI 17), Banff, Canada, May 2017.

Author(s) : H. Cai, Y. Wang, L. Alves de Barros Naviner and W. Zhao

Impact of the switching activity on the aging of delay-PUFs

ETS, Limassol, May 2017

Author(s) : N. Karimi, J.-L. Danger, F. Lozac'h and S. Guilley

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Codes for side-channel attacks and protections

2nd Int. Conf. on Codes, Cryptology and Information Security, in honor of Claude Carlet, Rabat, Marocco, April 2017, vol. 10194

Author(s) : S. Guilley, A. Heuser and O. Rioul

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Asymmetrical Length Biasing for Energy Efficient Digital Circuits

IEEE Latin American Symposium on Circuits and Systems, Bariloche, Argentina, February 2017.

Author(s) : F. Veirano, L. Alves de Barros Naviner and F. Silveira

Practical metrics for evaluation of fault-tolerant logic design

IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering , Saint Petersbourgh, Russia, February 2017, pp. 569-573.

Author(s) : A. Stempkovskiy, D. Telpukhov, R. Solovyev, E. Balaka and L. Alves de Barros Naviner

Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only)

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017, February 2017, pp. 295--296.

Author(s) : S. Chaudhuri

A User-Centric System for Verified Identities on the Bitcoin Blockchain

Data Privacy Management, Cryptocurrencies and Blockchain Technology - ESORICS 2017 International Workshops, DPM 2017 and CBT 2017, Oslo, Norway, September 14-15, 2017, Proceedings, 2017, pp. 390--407

Author(s) : D. Augot, H. Chabanne, Th. Chenevier, W. George and L. Lambert

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Verifiable Document Redacting

Computer Security - ESORICS 2017 - 22nd European Symposium on Research in Computer Security, Oslo, Norway, September 11-15, 2017, Proceedings, Part I, 2017, pp. 334--351

Author(s) : H. Chabanne, R. Hugel and J. Keuffer

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PhD Thesis and habilitations (HDR) - 2015 and 2014

1 Publication found for this search

Reliability Analysis of Spintronic Device Based Logic and Memory

Télécom ParisTech, February 2017, n° 2017-ENST-0005.

Author(s) : Y. Wang

Patents - 2015 and 2014

No publications found

Others - 2015 and 2014

No publications found
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